1. Field of the Invention
This invention generally relates to computer-aided design of integrated circuits and, more particularly, to path filtering mechanisms for static timing analysis.
2. Description of the Related Art
As tens of millions of gates are manufactured on wafers, software modeling of digital circuits is essential. Prototyping such a large and complex circuit is often prohibitively expensive and time-consuming. If a flaw is found in the prototyped circuit, the gates and interconnections are so small that probing the chip and determining a correction is almost impossible. Today""s Very Large Scale Integrated (VLSI) circuit designers, therefore, use software modeling to design and verify a circuit before fabrication.
The software modeling of circuits often includes a static timing analysis. A static timing analysis sums and compares delays relative to a pre-defined clock. The static timing analysis, for example, assures the designer that data does not arrive too late and remains stable long enough to be latched. A static timing analysis, however, is exhaustivexe2x80x94all paths within a circuit are analyzed for timing errors. Because a VLSI chip design has millions of interconnected gates, a static timing analysis traces millions of paths within the circuit. Some of these traced paths, however, may be architecturally falsexe2x80x94that is, paths that do not exist, or will never occur, within the physical circuit. Some of these traced paths may also be of lesser interest to the designer and, thus, xe2x80x9cmaskxe2x80x9d paths of higher interest.
Because the static timing analysis exhaustively traces all paths within a circuit design, static timing analysis tools include a filtering mechanism. The primary use of path filtering is to analyze a particular section of logic to efficiently correct errors. Static timing analyzers typically report only the top violating paths. Fixing the top error may leave a slightly better timing violation uncorrected. In fact the fix may actually make the masked path worse. To combat this a circuit designer will path filter the top violators to figure out a fundamental fix for an entire set of timing errors that may be related. Path filtering is used to identify this set of related errors.
The prior art filter mechanisms, however, do not work properly with latch-based circuit designs. A latch path that terminates at a latch exactly aliases with another latch path that flows through the latch while in a transparent mode. Current filtering algorithms, however, do not distinguish between latch paths sharing segments. Filtering mechanisms, therefore, similarly filter all latch paths, whether terminating at a latch or whether flowing through the latch.
There is, accordingly, a need in the art for filtering mechanisms for latch-based digital circuits that distinguish between paths that end at a latch from paths that flow through the latch, and for filtering mechanisms that are simple to use and quick to implement within static timing analyzers.
The aforementioned problems are solved by the present invention. The present invention describes an enhancement to existing path filtering mechanisms used in a static timing analysis. The present invention adds path termination information to path filtering statements. When paths are filtered during a static timing analysis, the addition of path termination information would specify where a path ends. The path termination information, therefore, distinguishes a path terminating at a transparent latch from another path flowing through the transparent latch. The present invention thus allows shorter segments to be filtered without filtering longer paths through latches.